KM684000A family cmos sram revision 2.0 february 1998 1 document title 512kx8 bit low power cmos static ram revision history the attached datasheets are provided by samsung electronics. samsung electronics co., ltd. reserve the right to change the spec ifications and products. samsung electronics will answer to your questions about device. if you have any questions, please contact the samsung branch offices. revision no. 0 .0 0.1 0.2 1.0 2.0 remark advance preliminary preliminary final final history initial draft revise revise - changed operating current i cc 2; 80ma ? 90ma finalize - change datasheet format ; one datasheet for commercial and industrial product. revise - change datasheet format - remove low power product from tsop package product - remove 100ns part form product draft date october 26, 1993 december 9, 1994 june 5, 1995 april 15, 1996 february 25, 1998
KM684000A family cmos sram revision 2.0 february 1998 2 512k x8 bit low power cmos static ram general description the KM684000A families are fabricated by samsung s advanced cmos process technology. the families support various operating temperature ranges and have various package types for user flexibility of system design. the fami- lies also supports low data retention voltage for battery back- up operation with low data retention current. features process technology : tft organization : 512kx8 power supply voltage : 4.5~5.5v low data retention voltage : 2v(min) three state output and ttl compatible package type : 32-dip-600, 32-sop-525, 32-tsop2-400f/r pin description pin name function cs chip select input oe output enable input we write enable input a 0 ~a 18 address inputs i/o 1 ~i/o 8 data inputs/outputs vcc power vss ground 32-dip 32-sop product family product family operating temperature vcc range(v) speed(ns) power dissipation pkg type standby (i sb1 , max) operating ( icc2 , max) KM684000Al commercial(0~70 c) 4.5~5.5 55/70ns 100 m a 90ma 32-dip, 32-sop 32-tsop2-f/r KM684000Al-l 20 m a KM684000Ali industrial(-40~85 c) 4.5~5.5 70ns 100 m a 32-sop 32-tsop2-f/r KM684000Ali-l 50 m a functional block diagram 32-tsop2-f a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 32-tsop2-r a16 a14 a12 a7 a6 a5 a4 a3 a2 a1 a0 i/o1 i/o2 i/o3 vss vcc a15 we a13 a8 a9 a11 oe a10 cs i/o8 i/o7 i/o6 i/o5 i/o4 32 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 a18 a17 a17 a18 samsung electronics co., ltd. reserves the right to change products and specifications without notice. a8 precharge circuit. memory array 1024 rows 512 8 columns i/o circuit column select clk gen. row select a2 a3 a11 a10 a15 a13 a17 a0 a1 a4 a5 a6 a7 a14 cs we i/o 1 data cont data cont oe i/o 8 a12 a16 a18 contri logic a9
KM684000A family cmos sram revision 2.0 february 1998 3 product list commercial temperature products(0~70 c) industrial temperature products(-40~85 c) part name function part name function KM684000Alp-5 KM684000Alp-5l KM684000Alp-7 KM684000Alp-7l KM684000Alg-5 KM684000Alg-5l KM684000Alg-7 KM684000Alg-7l KM684000Alt-5l KM684000Alt-7l KM684000Alr-5l KM684000Alr-7l 32-dip, 55ns, l-pwr 32-dip, 55ns, ll-pwr 32-dip, 70ns, l-pwr 32-dip, 70ns, ll-pwr 32-sop, 55ns, l-pwr 32-sop, 55ns, ll-pwr 32-sop, 70ns, l-pwr 32-sop, 70ns, ll-pwr 32-tsop2-f, 55ns, ll-pwr 32-tsop2-f, 70ns, ll-pwr 32-tsop2-r, 55ns, ll-pwr 32-tsop2-r, 70ns, ll-pwr KM684000Algi-7 KM684000Algi-7l KM684000Alti-7l KM684000Alri-7l 32-sop,70ns, l-pwr 32-sop, 70ns, ll-pwr 32-tsop2-f, 70ns, ll-pwr 32-tsop2-r, 70ns, ll-pwr functional description 1. x means don t care.(must be high or low state.) cs oe we i/o pin mode power h x 1) x 1) high-z deselected standby l h h high-z output disbaled active l l h dout read active l x 1) l din write active absolute maximum ratings 1) 1. stresses greater than those listed under "absolute maximum ratings" may cause permanent damage to the device. functional oper ation should be restricted to recommended operating condition. exposure to absolute maximum rating conditions for extended periods may affect r eliability. item symbol ratings unit remark voltage on any pin relative to vss v in ,v out -0.5 to 7.0 v - voltage on vcc supply relative to vss v cc -0.5 to 7.0 v - power dissipation p d 1.0 w - storage temperature t stg -65 to 150 c - operating temperature t a 0 to 70 c KM684000Al/l-l -40 to 85 c KM684000Ali/li-l soldering temperature and time t solder 260 c, 10sec (lead only) - -
KM684000A family cmos sram revision 2.0 february 1998 4 recommended dc operating conditions 1) note: 1. commercial product : t a =0 to 70 c, otherwise specified industrial product : t a =-40 to 85 c, otherwise specified 2. overshoot : v cc +3.0v in case of pulse width 30ns 3. undershoot : -3.0v in case of pulse width 30ns 4. overshoot and undershoot are sampled, not 100% tested. item symbol min typ max unit supply voltage vcc 4.5 5.0 5.5 v ground vss 0 0 0 v input high voltage v ih 2.2 - vcc+0.5v 2) v input low voltage v il -0.5 3) - 0.8 v capacitance 1) (f=1mhz, t a =25 c) 1. capacitance is sampled, not 100% tested item symbol test condition min max unit input capacitance c in v in =0v - 8 pf input/output capacitance c io v io =0v - 10 pf dc and operating characteristics item symbol test conditions min typ max unit input leakage current i li v in =vss to vcc -1 - 1 m a output leakage current i lo cs =v ih or oe =v ih or we =v il , v io =vss to vcc -1 - 1 m a operating power supply current i cc i io =0ma, cs =v il , v in =v il or v ih , read - - 15 ma average operating current i cc1 cycle time=1 m s, 100% duty, i io =0ma cs 0.2v, v in 3 0.2v or v in 3 vcc-0.2v read - - 15 ma write - - 35 i cc2 cycle time=min, 100% duty, i io =0ma, cs =v il, v in =v ih or v il - - 90 ma output low voltage v ol i ol =2.1ma - - 0.4 v output high voltage v oh i oh =-1.0ma 2.4 - - v standby current(ttl) i sb cs =v ih , other inputs=v il or v ih - - 3 ma standby current(cmos) i sb1 cs 3 vcc-0.2v, other inputs=0~vcc KM684000Al - - 100 m a KM684000Al-l - - 20 m a KM684000Ali - - 100 m a KM684000Ali-l - - 50 m a
KM684000A family cmos sram revision 2.0 february 1998 5 c l 1) 1. including scope and jig capacitance ac operating conditions test conditions (test load and test input/output reference) input pulse level : 0.8 to 2.4v input rising and falling time : 5ns input and output reference voltage : 1.5v output load (see right) :c l =100pf+1ttl ac characteristics (v cc =4.5~5.5v, KM684000A family:t a =0 to 70 c, KM684000Ai family:t a =-40to 85 c) parameter list symbol speed bins units 55ns 70ns min max min max read read cycle time t rc 55 - 70 - ns address access time t aa - 55 - 70 ns chip select to output t co - 55 - 70 ns output enable to valid output t oe - 25 - 35 ns chip select to low-z output t lz 10 - 10 - ns output enable to low-z output t olz 5 - 5 - ns chip disable to high-z output t hz 0 20 0 25 ns output disable to high-z output t ohz 0 20 0 25 ns output hold from address change t oh 10 - 10 - ns write write cycle time t wc 55 - 70 - ns chip select to end of write t cw 45 - 60 - ns address set-up time t as 0 - 0 - ns address valid to end of write t aw 45 - 60 - ns write pulse width t wp 40 - 50 - ns write recovery time t wr 0 - 0 - ns write to output high-z t whz 0 20 0 25 ns data to write time overlap t dw 25 - 30 - ns data hold from write time t dh 0 - 0 - ns end write to output low-z t ow 5 - 5 - ns data retention characteristics item symbol test condition min typ max unit vcc for data retention v dr cs 3 vcc-0.2v 2.0 - 5.5 v data retention current i dr vcc=3.0v, cs 3 vcc-0.2v KM684000Al - - 50 m a KM684000Al-l - - 15 KM684000Ali - - 50 KM684000Ali-l - - 20 data retention set-up time t sdr see data retention waveform 0 - - ms recovery time t rdr 5 - -
KM684000A family cmos sram revision 2.0 february 1998 6 address data out previous data valid data valid timming diagrams timing waveform of read cycle(1) (address controlled , cs = oe =v il , we =v ih ) t aa t rc t oh timing waveform of read cycle(2) ( we =v ih ) data valid high-z cs address oe data ou t notes (read cycle) 1. t hz and t ohz are defined as the time at which the outputs achieve the open circuit conditions and are not referenced to output voltage levels. 2. at any given temperature and voltage condition, t hz (max.) is less than t lz (min.) both for a given device and from device to device interconnection. t oh t aa t olz t lz t ohz t hz t rc t oe t co
KM684000A family cmos sram revision 2.0 february 1998 7 timing waveform of write cycle(2) ( cs controlled) address cs t wc t wr(4) t as(3) t dw t dh data valid we data in data out high-z high-z t cw(2) t wp(1) t aw notes (write cycle) 1. a write occurs during the overlap of a low cs and a low we . a write begins at the latest transition among cs going low and we going low : a write end at the earliest transition among cs going high and we going high, t wp is measured from the begining of write to the end of write. 2. t cw is measured from the cs going low to end of write. 3. t as is measured from the address valid to the beginning of write. 4. t wr is measured from the end of write to the address change. t wr applied in case a write ends as cs or we going high. data retention wave form cs controlled v cc 4.5v 2.2v v dr cs gnd data retention mode cs 3 v cc - 0.2v t sdr t rdr timing waveform of write cycle(1) (we controlled) address cs t cw(2) t wr(4) t wp(1) t dw t dh t ow t whz data undefined data valid we data in data out t wc t aw t as(3)
KM684000A family cmos sram revision 2.0 february 1998 8 package dimensions units : millimeter(inch) 0~15 1.91 #1 32 pin dual inline package (600mil) #32 13.60 0.20 0.535 0.008 41.91 0.20 1.650 0.008 ( ) 0.075 1 5 . 2 4 0 . 6 0 0 + 0.10 max 42.31 1.666 0.25 - 0.05 + 0.004 0.010 - 0.002 2.54 0.100 max 3.81 0.20 0.150 0.008 5.08 0.200 min 0.015 0.38 0.130 0.012 3.30 0.30 #16 #17 1.52 0.10 0.060 0.004 0.46 0.10 0.018 0.004 32 pin plastic small outline package (525mil) 0~8 #32 20.47 0.20 0.806 0.008 max 20.87 0.822 max 2.74 0.20 0.108 0.008 3.00 0.118 min 0.002 0.05 0.004 max 0.10 max #1 0.71 ( ) 0.028 1 3 . 3 4 0 . 5 2 5 11.43 0.20 0.450 0.008 0.80 0.20 0.031 0.008 + 0.10 0.20 - 0.05 + 0.004 0.008 - 0.002 14.12 0.30 0.556 0.012 #17 #16 1.27 0.050 + 0.100 0.41 - 0.050 + 0.004 0.016 - 0.002
KM684000A family cmos sram revision 2.0 february 1998 9 32 pin thin small outline package type ii (400f) 0~8 #32 20.95 0.10 0.825 0.004 max 21.35 0.841 max 1.00 0.10 0.039 0.004 1.20 0.047 min 0.002 0.05 0.004 max 0.10 max #1 0.95 ( ) 0.037 1 0 . 1 6 0 . 4 0 0 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 11.76 0.20 0.463 0.008 #17 #16 0.50 ( ) 0.020 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 1.27 0.050 0.40 0.10 0.016 0.004 package dimensions 32 pin thin small outline package type ii (400r) 0~8 #32 #1 1 0 . 1 6 0 . 4 0 0 + 0.10 0.15 - 0.05 + 0.004 0.006 - 0.002 11.76 0.20 0.463 0.008 #17 #16 0.50 ( ) 0.020 0.45 ~0.75 0.018 ~ 0.030 0.25 ( ) 0.010 20.95 0.10 0.825 0.004 max 21.35 0.841 max 1.00 0.10 0.039 0.004 1.20 0.047 min 0.002 0.05 0.004 max 0.10 max 0.95 ( ) 0.037 1.27 0.050 0.40 0.10 0.016 0.004 units : millimeter(inch)
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